This application is based upon and claims priority of Japanese Patent Application No. 2002-38550, filed in Feb. 15, 2002, the contents being incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, a semiconductor device having a ferroelectric capacitor and a method of manufacturing the same.
2. Description of the Prior Art
As the nonvolatile memory that still stores the information when the power supply is turned off, the ferroelectric random access memory (FeRAM) is known.
The FeRAM has a memory cell that stores the information using the hysteresis characteristic of the ferroelectric capacitor. The ferroelectric capacitor has the structure in which a ferroelectric film is formed between a pair of electrodes. In the ferroelectric capacitor, the polarization is generated in response to the magnitude of the voltage applied between the electrodes, and the spontaneous polarization is kept even when the applied voltage is removed. If the polarity of the applied voltage is reversed, the polarity of the spontaneous polarization is also reversed. Then, the information can be read by sensing the spontaneous polarization.
As the FeRAM memory cell, the 1T/1C type that uses one transistor and one capacitor to store 1-bit information and the 2T/2C type that uses two transistors and two capacitors to store 1-bit information are present. The 1T/1C type memory cell can reduce the cell area and achieve the higher integration in contrast to the 2T/2C type memory cell.
Next, steps of forming the 1T/1C type memory cell having the stacked capacitor is explained hereunder.
First, steps required to get a structure shown in FIG. 1A is explained.
An element isolation insulating film 102 is formed around an element forming region of a silicon substrate 101, and then a well 103 is formed in the element forming region. Then, two MOS transistors 104 are formed in the well 103.
The MOS transistor 104 has a gate electrode 104b formed on the well 103 via a gate insulating film 104a, and impurity diffusion regions 104c, 104d formed in the well 103 on both sides of the gate electrode 104b and serving as source/drain regions. Also, insulating sidewalls 105 used to form high impurity concentration regions 104d in the impurity diffusion regions 104c are formed on both side surfaces of the gate electrode 104b. 
Then, a transistor protection insulating film 106 for covering the MOS transistors 104 is formed on the silicon substrate 101, and then a first interlayer insulating film 107 is formed on the transistor protection insulating film 106.
Then, first contact hole 107a are formed in the first interlayer insulating film 107 on one impurity diffusion regions 104c of the MOS transistors 104, and then first contact plugs 108 are buried in the first contact hole 107a. 
Then, a first metal film 109, a ferroelectric film 110, and a second metal film 111 are formed sequentially on the first contact plugs 108 and the first interlayer insulating film 107.
Then, as shown in FIG. 1B, capacitors 112 are formed by patterning the first metal film 109, the ferroelectric film 110, and the second metal film 111 by virtue of the photography method. In the capacitor 112, the first metal film 109 is used as a lower electrode 109a, the ferroelectric film 110 is used as a dielectric film 110a, and the second metal film 111 is used as an upper electrode 111a. The capacitor 112 is the stacked type capacitor, and the lower electrode 109a is connected to one impurity diffusion layer 104c of the MOS transistor 104 via the underlying first contact plug 108.
Then, as shown in FIG. 1C, a single-layer capacitor protection film 113 is formed only once on the capacitors 112 and the first interlayer insulating film 107, then a second interlayer insulating film 114 is formed on the capacitor protection film 113, and then a second contact hole 114a is formed on the other impurity diffusion region 104d of the MOS transistors 104 by patterning the second interlayer insulating film 114, the capacitor protection film 113, the first interlayer insulating film 107, and the transistor protection insulating film 106 by virtue of the photolithography method. Then, a second contact plug 115 is formed in the second contact hole 114a. 
Next, steps required to form a structure shown in FIG. 1D will be explained hereunder.
Third contact holes 114b are formed on the upper electrodes 110a of the capacitors 112 by patterning the second interlayer insulating film 114. Then, a conductive film is formed on the second interlayer insulating film 114 and in the third contact holes 114b. Then, this conductive film is pattern to form wirings 116a, which are connected to the upper electrodes 111a of the capacitors 112, and at the same time to form a conductive pad 116b on the second contact plug 115.
Then, a third interlayer insulating film 117 for covering the wirings 116a and the conductive pad 116b is formed on the second interlayer insulating film 114. Then, a hole 117a is formed on the conductive pad 116b by patterning the third interlayer insulating film 117, and then a fourth conductive plug 118 is formed in the hole 117a. 
Then, a bit line 119 that is connected to the conductive plug 118 is formed on the third interlayer insulating film 117.
An arrangement of the MOS transistors, the capacitors, and the word line in the 1T/1C type memory cell, as described above, is given in a plan view of FIG. 2. In this case, FIG. 1D is a sectional view taken along a Ixe2x80x94I line in FIG. 2.
By the way, when the second contact hole 114a is opened in the first and second interlayer insulating films 107, 114, the alignment margin is required to prevent the contact of the second contact hole 114a to the capacitors 112. In this case, the second contact hole 114a must be separated from the capacitors 112 to such extent that the alignment margin can be assured. Accordingly, an interval between two capacitors 112 that are positioned adjacently over the well 103 is decided.
Unless such alignment margin is assured, it is possible that the second contact hole 114a overlaps with a part of the capacitors 112.
If the second contact hole 114a is formed to come into contact with the capacitors 112, the second contact plug 115 in the second contact hole 114a is short-circuited to the capacitors 112. Also, if the second contact hole 114a comes into contact with the capacitors 112, there is a possibility that, when the second contact plug 115 is formed by the CVD method, the ferroelectric film 110 is reduced by the reaction gas and thus the ferroelectric film 110 of the capacitor is degraded.
Also, if the area of the capacitor 112 is reduced to achieve the higher integration of the memory cell, the memory cell characteristic is ready to degrade.
It is an object of the present invention to provide a semiconductor device having a structure that is capable of reducing an alignment margin of a contact hole formed next to a capacitor, and a method of manufacturing the same.
The above subjects can be overcome by providing a semiconductor device that comprises a first impurity diffusion region formed in a semiconductor substrate; a first insulating layer formed over the semiconductor substrate; a capacitor formed on the first insulating layer and having a lower electrode, a ferroelectric layer, and an upper electrode; an insulating capacitor protection layer made of material that is different from the first insulating layer, for covering an upper surface and a side surface of the capacitor; a second insulating layer formed on the capacitor protection layer and the first insulating layer, and made of material that can be etched selectively from the capacitor protection layer; a first hole formed in the second insulating layer and positioned next to the side surface of the capacitor via the capacitor protection layer; and a first conductive plug formed in the first hole and connected electrically to the first impurity diffusion region.
Also, the above subjects can be overcome by providing a semiconductor device manufacturing method that comprises the steps of forming a first impurity diffusion region in a semiconductor substrate; forming a first insulating layer over the semiconductor substrate; forming a first conductive layer, a ferroelectric layer, and a second conductive layer on the first insulating layer; forming a capacitor by patterning the second conductive layer, the ferroelectric layer, and the first conductive layer using a first mask; forming an insulating capacitor protection layer made of material, which is different from the first insulating layer, on an upper surface and side surfaces of the capacitor; forming a second insulating layer made of material, that can be etched selectively from the capacitor protection layer, on the capacitor protection layer and the first insulating layer; forming a first hole, which comes into contact with the capacitor protection layer on the side surface of the capacitor, in the second insulating layer; and forming a first conductive plug, which is connected electrically to the first impurity diffusion region, in the first hole.
According to the semiconductor device of the present invention, there are provided the capacitor protection film for covering the upper surface and the side surface of the ferroelectric capacitor that is formed on the first insulating film, the hole formed in the second insulating film, which is formed on the capacitor protection film and the first insulating film, to be positioned adjacently to the side surface of the ferroelectric capacitor via the capacitor protection film, and the conductive plug formed in the hole.
Accordingly, the interval between the ferroelectric capacitor and the conductive plug is set equally to the thickness of the capacitor protection film, and thus the capacitor area is widened rather than the prior art because the forming area of the ferroelectric capacitor approaches the hole.
Also, according to the semiconductor device manufacturing method of the present invention, there are provided the steps of covering the upper surface and the side surface of the ferroelectric capacitor, that is formed on a first insulating film, with the capacitor protection film, then forming a second insulating film made of material, which can be etched selectively from the capacitor protection films, on the capacitor protection films and the first insulating film, then forming the hole in a second insulating film to come into contact with the capacitor protection film, and then forming the conductive plug in the hole.
Accordingly, in the step of forming the hole in the second insulating film, the hole is positioned in a self-alignment while using the capacitor protection film on the surface of the ferroelectric capacitor. Therefore, it is not necessary to secure the alignment margin to form the hole widely in advance, and the formation of the hole is facilitated, and the formation region of the ferroelectric capacitor is extended toward the hole by positioning the hole closer to the capacitor than the prior art.
In this case, the capacitor protection film consists of the material which prevents the capacitor from the reduction, and which etches the insulating film selectively to the capacitor protection film.